FPGA On-Chip Debugging, (OCD). DiaLite enables engineers to test and to debug their FPGA design at the prototype level.

Prototype bring-up, debugging

DiaLite Leading Edge (DiaLite LE) is an On-Chip instrumentation tool that sets a new way to monitor and debug complex designs for any type of FPGA. With DiaLite, you simply choose test IPs like triggers or logic analyzers that you seamlessly embed into your design. Once your usual flow is performed (Synthesis, Placing, Routing), you can run your design with its embedded instrumentation. DiaLite allows you to monitor your instruments, analyze logic signals and transactions, record logic events data and much more !

• Librairie complète d’instruments fournie par l’édition Leading Edge
• Débogueur RTL avec possibilité d’insérer des points d’arrêt
• Insertion manuel ou automatique
• Possibilité de placer des points d’arrêt lorsque le code tourne sur le silicium
• Visualisation pas à pas de l’exécution
• Visualisation simultanée du code HDL et des signaux
• Débogueur de bus AMBA
• Possibilité de stocker les données sur une mémoire externe

JTAG – Embedded instrumentation

• Multi-FPGA vendons
• Multi-Synthesis tools
• Multi-languages VHDL (1076.1) and Verilog (1364)
• Library of Debug IPs
• Easy tool start-up séquence
• User Friendly Interface
• Supported by intuitive, generic software interface with built-in sequencer

Engineering designers, FPGA and SOC rapid prototyping developments

You can fill out the form with a description of your needs or you can send an email to sales@temento.com. A reply will be sent within 24 hours.

FPGA On-Chip Debugging, (OCD). DiaLite enables engineers to test and to debug their FPGA design at the prototype level.

Prototype bring-up, debugging.

DiaLite™ Power Edge (DiaLite PE) provides an unrivaled environment and collection of debug IPs to verify and debug your FPGA based system designs. In addition to DiaLite Leading Edge features, DLI Power Edge provided a complete RTL debugging environment called HDL Fault Finder. This environment enables to insert watch points in the RTL code and to trigger signal values on silicon using breakpoints features.

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• Trace and check AMBA Bus Transaction On-Chip

is an On-Chip instrumentation tool that sets a new way to monitor and debug complex designs for any type of FPGA. With DiaLite, you simply choose test IPs like triggers or logic analyzers that you seamlessly embed into your design. Once your usual flow is performed (Synthesis, Placing, Routing), you can run your design with its embedded instrumentation. DiaLite allows you to monitor your instruments, analyze logic signals and transactions, record logic events data and much more !

DiaLite™ Power Edge provides an unrivaled environment and collection of test

IPs to verify and debug your FPGA based system designs:

• Trigger on design signal values and sample them at Design Speed
• Run RTL Code Debugger interface to your FPGA Design
• Trace and check AMBA Bus Transaction On-Chip

• Leading Edge edition features
• Automatic & manual Watchpoints insertion
• Convert any Watchpoints into a Breakpoint during the debugging phase
• Set Breakpoints either on instruments or on your code
• Step-by-step code execution, recording and display
• Concurrent events recording and display
• Trace and debugging capability up to the instance level
• Automatic display of the trace on Breakpoint
• Dual display of HDL code vs. waveforms

JTAG – Embedded instrumentation

• A unique productivity and flexibility when combining the instruments, associating signal instruments and code fault finder or even embedding assertions
• The widest choice of instruments (15 instruments among 6 families of IP)
• Off-Chip instrumentation allows to store high amount of test data traces outside the FPGA target
• Multi-FPGA vendons
• Multi-Synthesis tools
• Multi-languages VHDL (1076.1) and Verilog (1364)

Engineering designers, FPGA and SOC rapid prototyping developments

You can fill out the form with a description of your needs or you can send an email to sales@temento.com. A reply will be sent within 24 hours.

FPGA On-Chip Debugging, (OCD). DiaLite™ Platform (DiaLite PT) enables engineers to test and to debug their FPGA design at the prototype level.

Prototype bring-up, debugging.

DiaLite™ Platform is the most complete and powerful tool available on the market to verify and debug your SoC or FPGA. In addition to Power Edge features, DLI Platform edition enable to verify the design implementation by reusing Assertions developed during the development process.

• DiaLite Power Edge Features
• PSL / SVA standards, On-Chip Real-Time and Real-Speed verification
• Reuse of your formal verification coming from “Assertion Based” CAD tools
• Timing oriented verification (Ex: Protocol State Machine)
• VHDL / Verilog generation, automatic IP connection & insertion
• In-depth observation without numerous synthesis looks
• Ensure test coverage of corner cases or bugs that would have remained undetected
• Measure functional coverage & get statistics on the verification process (cover directive)
• Find bugs earlier in the design cycle

JTAG – Embedded instrumentation

• Reduce the verification time by detecting bugs earlier
• Isolating where a bug is located
• Improve the efficiency by improving reuse
• Multi-vendor independent platform
• Multi-languages PSL and System Verilog
• Easy tool start-up séquence
• User Friendly Interface
• Supported by intuitive, generic software interface with built-in sequencer

Engineering designers, FPGA and SOC rapid prototyping developments

You can fill out the form with a description of your needs or you can send an email to sales@temento.com. A reply will be sent within 24 hours.