TEMENTO SYSTEMS INVESTS IN THE RESEARCH AND DEVELOPMENT OF NEW TECHNOLOGIES TO IMPROVE THE TESTING AND VERIFICATION OF ELECTRONIC SYSTEMS. THE PRODUCTS RESULTING FROM THIS WORK WILL ADD AND ENHANCE OUR EXISTING PRODUCT OFFERINGS TO BETTER SUPPORT OUR CUSTOMERS.
ETBV aims to develop a tool that allows to design a physical verification environment on FPGA (*).
FPGA component verification becomes a major issue with the development of embedded and connected objects. Increasing the complexity of logical functions (multi-core processors, IP, heterogeneous systems, etc.).
Besides that, the implementation of RTCA/DO-254, Design Assurance Guidance for Airborne Electronic Hardware standard or IEC 62566 to achieve highly reliable "HDL-Programmed Devices" , require developing new methodologies, algorithms and tools capable of meeting these requirements.
It is therefore imperative to develop innovative technologies allowing the user to overcome the constraints related to the physical verification of FPGA non-intrusive mode.
The purpose of our work is to provide our customers with a solution that can add significant value to verifying designs on FPGAs and associated applications.
(*) ETBV is supported by BPI France
Harden the multi-core FPGA components against ionizing radiations.
Cosmic radiations can disrupt the functioning of electronic components embedded in planes, spacecraft and sometimes even on the ground
These systems experience an exponential demand in terms of performance, while having to provide guarantees in terms of dependability and reliability. However, the level of integration of these processors, associated with a sharp reduction in their size, makes them more sensitive to radiation of natural origin (storm, high temperature, etc.) or artificial radiation.
Launched at the initiative of the Direction Générale de l’Armement (DGA), the objective of this project is to develop a software design flow capable of improving the fault tolerance of multi-core processors on FPGA for critical applications. lNRIA - French Institute for Research in Computer Science and Automation), ONERA - Office National d’Etudes et de Recherches Aérospatiales and Temento Systems have come together to respond to this initiative and to develop solutions adapted to these new requirements.
Detailed information on this work is available on the website https://www.flodam.fr
Develop and manage test infrastructures (IP) embedded in integrated circuits and electronic cards.
Supported by the EUREKA PENTA (*) cluster, the HADES project aims to develop a hierarchical test infrastructure in integrated circuits and electronic systems.
The project goal is to develop an infrastructure enabling on-line safe and secure measurements, putting in place hierarchical tests for integrated circuits and electronic systems and thereby, guarantee high performance and on-line self-testing in a secure environment. The project envisions creating benefit at system and user levels thanks to the test infrastructure reused for hierarchical on-line tests in the respective field of application.
Detailed information on this project is available on the website https://www.project-hades.eu
(*) About PENTA
PENTA is a program dedicated to components and systems based on micro and nano-electronics. It has been put in place to meet the needs of the industry, covering all phases of development - from TRL 2 to pilot production or service launch (TRL8).